Conventional metal-oxide-semiconductor (MOS) transistors often use metal silicide layers to reduce resistance. A self aligned silicidation process (salicide) is often used to form the region of titanium, cobalt or tungsten silicide on the gate electrode and source/drain regions of the MOS transistor. In this process, a blanket metal film is deposited on the silicon substrate containing the MOS transistor structure. The metal is then reacted with the underlying silicon regions to form a low resistance metal silicide. Any unreacted metal remaining on the substrate is then removed using a metal etch process that is selective to the remaining metal silicide.
During this process it is critical that the metal silicide is confined to the source/drain and gate regions. In the case of the source/drain regions, if the metal silicide forms under the transistor sidewall structures, the transistors could become inoperable. Furthermore the metal silicide layer should form a relatively smooth interface with the underlying source/drain region. Any unevenness in the metal silicide source/drain interface will lead to increased leakage currents and reduced breakdown voltages.
In order to reduce the resistances associated with the metal silicide regions, nickel is finding increasing use in forming the metal silicide regions in MOS transistors, particularly for transistors with physical gate lengths of less than 40 nm and/or MOS transistors with ultra-shallow junctions. Nickel has a very high diffusivity in silicon leading to the formation of nickel silicide regions that extend beneath the transistor sidewall structures. In addition, nickel silicide regions formed using existing methods have a very rough interface with underlying p-type source/drain regions. As described above, this results in transistors with higher leakage currents and reduced breakdown voltages.
There is therefore a need for a method to form metal silicide regions on the gate electrode and source/drain regions of a MOS transistor that have a smooth interface with the underlying source/drain region as well as not extend under the transistor sidewall structures.